1. Field of the Invention
The present invention relates to a semiconductor memory integrated circuit such as an SRAM (static random access memory), and in particular, relates to a semiconductor memory integrated circuit whose operation can be selected between a high-speed operation and a low power consumption operation, wherein switching therebetween can be easily performed.
Priority is claimed on Japanese Patent Application No. 2007-034766, filed Feb. 15, 2007, the contents of which are incorporated herein by reference.
2. Description of the Related Art
FIG. 9 is a diagram showing the structure of the address controller of a conventional SRAM. As shown in FIG. 9, in the relevant semiconductor memory integrated circuit, each bank has an X-row controller 1A, an X predecoder 2, and an X decoder 3, and is selected by a bank active signal (i.e., BANK-ACT signal). In the bank selected by the bank active signal, the x address, read by the X-row controller 1A, is decoded step by step via the X predecoder 2 and the X decoder 3, so that a signal used for selecting a memory cell is generated.
FIG. 10 is a diagram showing the structure of the X-row controller 1A in the conventional structure. The X-row controller 1A consists of a latch circuit 11 and a high-speed-operation control circuit 12. An X address signal B is read and stored (or held) by the latch circuit 11. The X address stored by the latch circuit 11 is sent as an X address signal E to the X predecoder 2. The structure and operation of both the latch circuit 11 and the high-speed operation control circuit 12 will be explained in detail when describing an embodiment of the present invention.
As shown in FIG. 10, in the conventional X-row controller 1A, except for the latch circuit 11, only the high-speed operation control circuit 12 used for performing high-speed operation is present. In this case, in the X-row controller 1A, the X address signal B is stored by the latch circuit 11 and is output to the predecoder 2, regardless of a bank active signal A. Therefore, in each bank which is not selected by the bank active signal A, even the internal circuit of each non-selected X predecoder is activated by a change in the X address signal. Such a method in which the X address is not controlled by the bank active signal A is advantageous when performing a high-speed operation with respect to tRCD (active to read or write command delay) or the like. However, as the internal circuit of each non-selected X predecoder also operates, power (i.e., electric current) is unnecessarily consumed.
Conventionally, a refresh control circuit and a refresh control system are also known (e.g., see Patent Document 1). However, the relevant conventional technique relates to a system for controlling a DRAM by using a plurality of control circuits, and is used to provide a refresh control circuit for performing an operation during a refresh time as quickly as possible, thereby improving the system performance. That is, the conventional technique is not used to resolve the above-described problem, and thus has an objective and a structure different from those of the present invention, as described later.
Also, a semiconductor integrated circuit and a test method thereof are known conventionally, and disclosed in Patent Document 2. However, the relevant conventional technique is used to provide a semiconductor integrated circuit and a test method thereof, by which a high failure-detection rate can be obtained without increasing the circuit area, and each test pattern can be easily formed. Therefore, this technique is also not used to resolve the above-described problem, and thus has a purpose and a structure different from those of the present invention.
A semiconductor integrated circuit and a method of controlling characteristics thereof are also known conventionally, as disclosed in Patent Document 3. However, the relevant conventional technique relates to a semiconductor integrated circuit having an internal circuit whose characteristics can be controlled using a ROM circuit including a fuse or the like, and is used to restore the original characteristics changed by a control of the ROM circuit. Therefore, this technique also is also not used to resolve the above-described problem, and thus has a purpose and a structure different from those of the present invention.
A semiconductor memory integrated circuit is also known conventionally, as disclosed in Patent Document 4. However, the relevant conventional technique is used to provide a semiconductor memory integrated circuit having reduced logic stages between clock input and word-line activation, so as to provide high-speed operation. Therefore, this technique is also not used to resolve the above-described problem, and thus has a purpose and a structure different from those of the present invention.    Patent Document 1: Japanese Unexamined Patent Application, First Publication No. H9-320264.    Patent Document 2: Japanese Unexamined Patent Application, First Publication No. H11-118883.    Patent Document 3: Japanese Unexamined Patent Application, First Publication No. 2001-216800.    Patent Document 4: Japanese Unexamined Patent Application, First Publication No. 2001-344978.
As described above, in the X-row controller of the conventional semiconductor integrated circuit, the X address signal is stored by the latch circuit and then output to the X predecoder, regardless of the bank active signal. Therefore, the internal circuit of the X predecoder in each non-selected bank operates, thereby unnecessarily consuming power.